How do you calculate 555 astable frequency and duty cycle?

The capacitor charges through R1 + R2 from 1/3 V_CC to 2/3 V_CC while the output is high, t_H = 0.693(R1+R2)C, then discharges through R2 and the internal discharge transistor from 2/3 to 1/3 V_CC while the output is low, t_L = 0.693·R2·C. So f = 1/(t_H + t_L) = 1.44/((R1+2R2)C) and D = (R1+R2)/(R1+2R2). The 0.693 is ln 2, because each half-cycle moves halfway between the start voltage and the target. With R1 = 10 kΩ, R2 = 47 kΩ and C = 10 µF, f ≈ 1.39 Hz and D ≈ 55%.

Why is the duty cycle always above 50%, and how do I get less?

Charging goes through R1 + R2 but discharging only through R2, so t_H is always longer than t_L and the duty cycle is above 50% (approaching 50% when R1 is much smaller than R2). Put a diode across R2, anode to pin 7 and cathode to pins 6/2: the charging current bypasses R2, so t_H ≈ 0.693·R1·C, while discharge still goes through R2 with t_L = 0.693·R2·C. Choose R1 < R2 for a duty cycle under 50%. The diode drop makes t_H slightly longer, and the tool uses the exact formula including it.

How does the 555 work inside?

Three internal 5 kΩ resistors divide the supply into 2/3 V_CC and 1/3 V_CC references. When the threshold pin 6 rises above 2/3 V_CC, the upper comparator resets the SR flip-flop: output pin 3 goes low and the discharge transistor pulls pin 7 to ground. When the trigger pin 2 falls below 1/3 V_CC, the lower comparator sets the flip-flop: the output goes high and the discharge transistor turns off. An astable circuit simply lets the capacitor voltage bounce between the two thresholds. The CV pin 5 connects to the 2/3 node, so an external voltage there moves both thresholds.

Why is the monostable pulse width 1.1RC?

Before triggering, the discharge transistor holds the capacitor at 0 V. A trigger sets the output high and turns the transistor off, so the capacitor charges through R from 0 toward V_CC; at 2/3 V_CC the upper comparator resets the flip-flop and the pulse ends. From V_CC(1 − e^(−t/RC)) = 2/3 V_CC you get t = RC·ln 3 ≈ 1.0986RC, usually written 1.1RC; R = 100 kΩ with C = 10 µF gives about 1.1 s. Triggers during the pulse are ignored by the NE555, but if the trigger input is held low past the end of the pulse the output stays high.

What should I watch out for when choosing parts?

Keep resistors roughly between 1 kΩ and 1 MΩ. If R1 is too small, the supply drives a large current through R1 into the discharge transistor; if the resistors are too large, comparator input current and capacitor leakage spoil the timing. Electrolytic capacitors are often ±20%, so use film capacitors for accurate timing and decouple pin 5 with 10 nF to ground. The bipolar NE555 output high level sits about 1.7 V below V_CC; CMOS versions such as the TLC555 or 7555 use less power, run faster and swing close to the rails.

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⏱️555 Timer Calculator - Astable Frequency, Monostable, Internal Diagram

Q: How does the 555 work inside?

Three internal 5 kΩ resistors divide the supply into 2/3 V_CC and 1/3 V_CC references. When the threshold pin 6 rises above 2/3 V_CC, the upper comparator resets the SR flip-flop: output pin 3 goes low and the discharge transistor pulls pin 7 to ground. When the trigger pin 2 falls below 1/3 V_CC, the lower comparator sets the flip-flop: the output goes high and the discharge transistor turns off. An astable circuit simply lets the capacitor voltage bounce between the two thresholds. The CV pin 5 connects to the 2/3 node, so an external voltage there moves both thresholds.

Q: Why is the monostable pulse width 1.1RC?

Before triggering, the discharge transistor holds the capacitor at 0 V. A trigger sets the output high and turns the transistor off, so the capacitor charges through R from 0 toward V_CC; at 2/3 V_CC the upper comparator resets the flip-flop and the pulse ends. From V_CC(1 − e^(−t/RC)) = 2/3 V_CC you get t = RC·ln 3 ≈ 1.0986RC, usually written 1.1RC; R = 100 kΩ with C = 10 µF gives about 1.1 s. Triggers during the pulse are ignored by the NE555, but if the trigger input is held low past the end of the pulse the output stays high.

Q: What should I watch out for when choosing parts?

Keep resistors roughly between 1 kΩ and 1 MΩ. If R1 is too small, the supply drives a large current through R1 into the discharge transistor; if the resistors are too large, comparator input current and capacitor leakage spoil the timing. Electrolytic capacitors are often ±20%, so use film capacitors for accurate timing and decouple pin 5 with 10 nF to ground. The bipolar NE555 output high level sits about 1.7 V below V_CC; CMOS versions such as the TLC555 or 7555 use less power, run faster and swing close to the rails.

This tool opens up the 555 timer. The internal block diagram shows the three 5 kΩ divider resistors, the upper and lower comparators, the SR flip-flop and the discharge transistor, with every signal turning red when it is high; a capacitor level bar and an LED on the output follow along, and the capacitor and output waveforms scroll in sync below. In astable mode you set R1, R2, C, the supply and the CV voltage and get frequency, period, high and low times and duty cycle; add a diode across R2 for less than 50% duty, and listen to the frequency when it is audible. In monostable mode a trigger button fires a 1.1RC pulse. The picker tab searches standard E-series values for the best match to a target frequency and duty cycle, or a pulse width.

Free · No sign-up · Runs in your browserLast updated: 2026-10-29

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How to use 555 Timer Calculator & Simulator

1In Astable, set V_CC, R1, R2 and C and watch the block diagram, capacitor voltage and output
2Tick the diode option for a duty cycle under 50%, or drive the CV pin to make a VCO
3In Monostable, set R and C and press Trigger to see the t = 1.1RC pulse
4In the Component picker, enter a target frequency and duty cycle (or pulse width) and load a suggestion back into the circuit

FAQ

How do you calculate 555 astable frequency and duty cycle?: The capacitor charges through R1 + R2 from 1/3 V_CC to 2/3 V_CC while the output is high, t_H = 0.693(R1+R2)C, then discharges through R2 and the internal discharge transistor from 2/3 to 1/3 V_CC while the output is low, t_L = 0.693·R2·C. So f = 1/(t_H + t_L) = 1.44/((R1+2R2)C) and D = (R1+R2)/(R1+2R2). The 0.693 is ln 2, because each half-cycle moves halfway between the start voltage and the target. With R1 = 10 kΩ, R2 = 47 kΩ and C = 10 µF, f ≈ 1.39 Hz and D ≈ 55%.
Why is the duty cycle always above 50%, and how do I get less?: Charging goes through R1 + R2 but discharging only through R2, so t_H is always longer than t_L and the duty cycle is above 50% (approaching 50% when R1 is much smaller than R2). Put a diode across R2, anode to pin 7 and cathode to pins 6/2: the charging current bypasses R2, so t_H ≈ 0.693·R1·C, while discharge still goes through R2 with t_L = 0.693·R2·C. Choose R1 < R2 for a duty cycle under 50%. The diode drop makes t_H slightly longer, and the tool uses the exact formula including it.
How does the 555 work inside?: Three internal 5 kΩ resistors divide the supply into 2/3 V_CC and 1/3 V_CC references. When the threshold pin 6 rises above 2/3 V_CC, the upper comparator resets the SR flip-flop: output pin 3 goes low and the discharge transistor pulls pin 7 to ground. When the trigger pin 2 falls below 1/3 V_CC, the lower comparator sets the flip-flop: the output goes high and the discharge transistor turns off. An astable circuit simply lets the capacitor voltage bounce between the two thresholds. The CV pin 5 connects to the 2/3 node, so an external voltage there moves both thresholds.
Why is the monostable pulse width 1.1RC?: Before triggering, the discharge transistor holds the capacitor at 0 V. A trigger sets the output high and turns the transistor off, so the capacitor charges through R from 0 toward V_CC; at 2/3 V_CC the upper comparator resets the flip-flop and the pulse ends. From V_CC(1 − e^(−t/RC)) = 2/3 V_CC you get t = RC·ln 3 ≈ 1.0986RC, usually written 1.1RC; R = 100 kΩ with C = 10 µF gives about 1.1 s. Triggers during the pulse are ignored by the NE555, but if the trigger input is held low past the end of the pulse the output stays high.
What should I watch out for when choosing parts?: Keep resistors roughly between 1 kΩ and 1 MΩ. If R1 is too small, the supply drives a large current through R1 into the discharge transistor; if the resistors are too large, comparator input current and capacitor leakage spoil the timing. Electrolytic capacitors are often ±20%, so use film capacitors for accurate timing and decouple pin 5 with 10 nF to ground. The bipolar NE555 output high level sits about 1.7 V below V_CC; CMOS versions such as the TLC555 or 7555 use less power, run faster and swing close to the rails.

Features

Animated internal diagram: comparators, SR flip-flop, discharge transistor and output stage highlighted in real time, synced with the waveform cursor
Exact astable timing: t_H, t_L, the longer first cycle after power-up and duty cycle, compared with the textbook 1.44/((R1+2R2)C)
Diode across R2 (with its 0.7 V drop) for under 50% duty, and a CV pin input to shift the thresholds
Monostable trigger button showing the 1.1RC delay and non-retriggerable behaviour
E6/E12/E24 component picker ranked by frequency and duty error, with one-click load
LED flasher view (looks steady above about 25 Hz in real time) and a duty-cycle-accurate audio tone

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